Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique

Hyoseong Choi; Jiwon Lee; Jeonghoon Choi; Won Woo Ro

doi:10.1109/ITC-CSCC55581.2022.9894856

Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique

Hyoseong Choi, Jiwon Lee, Jeonghoon Choi, Won Woo Ro

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

AI and big data applications with large memory footprints are rapidly increasing. The memory footprint of applications may exceed the main memory, and accordingly, the need for high-speed processing of large data is increasing. This paper proposes a method to utilize a DRAM-based Network of DRAM (NoD) as a swap space. The Swap transfers data in units of 4KB pages, and conventionally, disks use 512 or 4096 bytes as a minimum data access unit. However, by utilizing DRAM's byte-addressability characteristic and latency hiding technique, necessary data can be read from the swap space in 64 bytes. For NoD architecture verification, a full system experiment environment is built using gem5 and DRAMsim3 simulators. For applications with frequent swap operations (XSBench, HPCG, and Ibm), the proposed technique achieves an average performance improvement of 12.3%.

Original language	English
Title of host publication	ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	239-242
Number of pages	4
ISBN (Electronic)	9781665485593
DOIs	https://doi.org/10.1109/ITC-CSCC55581.2022.9894856
Publication status	Published - 2022
Event	37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022 - Phuket, Thailand Duration: 2022 Jul 5 → 2022 Jul 8

Publication series

Name	ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference	37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022
Country/Territory	Thailand
City	Phuket
Period	22/7/5 → 22/7/8

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

Information Systems
Electrical and Electronic Engineering
Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Hardware and Architecture

Access to Document

10.1109/ITC-CSCC55581.2022.9894856

Cite this

Choi, H., Lee, J., Choi, J., & Ro, W. W. (2022). Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique. In ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications (pp. 239-242). (ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC55581.2022.9894856

Choi, Hyoseong ; Lee, Jiwon ; Choi, Jeonghoon et al. / Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique. ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 239-242 (ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications).

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title = "Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique",

abstract = "AI and big data applications with large memory footprints are rapidly increasing. The memory footprint of applications may exceed the main memory, and accordingly, the need for high-speed processing of large data is increasing. This paper proposes a method to utilize a DRAM-based Network of DRAM (NoD) as a swap space. The Swap transfers data in units of 4KB pages, and conventionally, disks use 512 or 4096 bytes as a minimum data access unit. However, by utilizing DRAM's byte-addressability characteristic and latency hiding technique, necessary data can be read from the swap space in 64 bytes. For NoD architecture verification, a full system experiment environment is built using gem5 and DRAMsim3 simulators. For applications with frequent swap operations (XSBench, HPCG, and Ibm), the proposed technique achieves an average performance improvement of 12.3%.",

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Choi, H, Lee, J, Choi, J & Ro, WW 2022, Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique. in ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications. ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications, Institute of Electrical and Electronics Engineers Inc., pp. 239-242, 37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022, Phuket, Thailand, 22/7/5. https://doi.org/10.1109/ITC-CSCC55581.2022.9894856

Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique. / Choi, Hyoseong; Lee, Jiwon; Choi, Jeonghoon et al.
ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., 2022. p. 239-242 (ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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PY - 2022

Y1 - 2022

N2 - AI and big data applications with large memory footprints are rapidly increasing. The memory footprint of applications may exceed the main memory, and accordingly, the need for high-speed processing of large data is increasing. This paper proposes a method to utilize a DRAM-based Network of DRAM (NoD) as a swap space. The Swap transfers data in units of 4KB pages, and conventionally, disks use 512 or 4096 bytes as a minimum data access unit. However, by utilizing DRAM's byte-addressability characteristic and latency hiding technique, necessary data can be read from the swap space in 64 bytes. For NoD architecture verification, a full system experiment environment is built using gem5 and DRAMsim3 simulators. For applications with frequent swap operations (XSBench, HPCG, and Ibm), the proposed technique achieves an average performance improvement of 12.3%.

AB - AI and big data applications with large memory footprints are rapidly increasing. The memory footprint of applications may exceed the main memory, and accordingly, the need for high-speed processing of large data is increasing. This paper proposes a method to utilize a DRAM-based Network of DRAM (NoD) as a swap space. The Swap transfers data in units of 4KB pages, and conventionally, disks use 512 or 4096 bytes as a minimum data access unit. However, by utilizing DRAM's byte-addressability characteristic and latency hiding technique, necessary data can be read from the swap space in 64 bytes. For NoD architecture verification, a full system experiment environment is built using gem5 and DRAMsim3 simulators. For applications with frequent swap operations (XSBench, HPCG, and Ibm), the proposed technique achieves an average performance improvement of 12.3%.

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Choi H, Lee J, Choi J, Ro WW. Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique. In ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc. 2022. p. 239-242. (ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications). doi: 10.1109/ITC-CSCC55581.2022.9894856

Analysis of DRAM-based Network of DRAM Swap Space Adopting Latency Hiding Technique

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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