Analysis of a novel Elevated Source Drain MOSFET with reduced gate-induced drain-leakage current

Engineering

• Gate Induced Drain Leakage 100%
• Etching Process 33%
• Electric Field 33%
• Side Wall 33%
• Dry Etching 33%
• Channel Depth 33%
• Activation 33%
• Energy Engineering 33%

Physics

• Region 66%
• Electric Fields 33%
• Ion Implantation 33%
• Sides 33%
• Width 33%