An on-chip error detection method to reduce the post-silicon debug time

Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

Original languageEnglish
Article number7464321
Pages (from-to)38-44
Number of pages7
JournalIEEE Transactions on Computers
Issue number1
Publication statusPublished - 2017 Jan 1

Bibliographical note

Publisher Copyright:
© 1968-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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