TY - GEN
T1 - An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC
AU - Lee, Yong
AU - Seo, Sungyoul
AU - Kang, Sungho
PY - 2013
Y1 - 2013
N2 - RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.
AB - RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.
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U2 - 10.1109/ISOCC.2013.6863965
DO - 10.1109/ISOCC.2013.6863965
M3 - Conference contribution
AN - SCOPUS:84906918573
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 176
EP - 179
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -