Abstract
In this paper, we propose an efficient bit loading algorithm for IEEE 802.11a wireless LAN systems. A conventional bit loading algorithm uses the SNR value of each subcarrier. However, it is very difficult to estimate the exact SNR value in wireless LAN systems due to the randomness of AWGN. Therefore, the proposed algorithm uses the channel frequency response instead of the SNR value of each subcarrier. From 54Mbps simulation, we can obtain the performance gain of 6.5dB at PER of 10"2 with the proposed algorithm, whereas the conventional one obtains that of 5dB at the same conditions. Also, it is observed that the wireless LAN system with the proposed algorithm supports up to 63Mbps. After the logic synthesis using 0.35um CMOS technology, the logic gate count for the processor with the proposed algorithm can be reduced by 34% in comparison with the conventional one.
Original language | English |
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Title of host publication | ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings |
Editors | Ting-Ao Tang, Wenhong Li, Huihua Yu |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1054-1057 |
Number of pages | 4 |
ISBN (Electronic) | 078037889X |
DOIs | |
Publication status | Published - 2003 |
Event | 5th International Conference on ASIC, ASICON 2003 - Beijing, China Duration: 2003 Oct 21 → 2003 Oct 24 |
Publication series
Name | IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings |
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Volume | 2 |
ISSN (Print) | 1523-553X |
Conference
Conference | 5th International Conference on ASIC, ASICON 2003 |
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Country/Territory | China |
City | Beijing |
Period | 03/10/21 → 03/10/24 |
Bibliographical note
Publisher Copyright:© 2003 IEEE
All Science Journal Classification (ASJC) codes
- Engineering(all)