An Efficient Architecture of In-Loop Filters for Multicore Scalable HEVC Hardware Decoders

Hyun Mi Kim, Jeong Gil Ko, Seongmo Park

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


This paper proposes an efficient architecture of HEVC in-loop filters (ILFs) with the target of providing effective multicore utilization for ultra-high definition video applications. While HEVC allows for a high level of parallelization, the issue of data dependencies at the ILF leads to inefficient parallel processing performance. The novel memory organization and management techniques address the data dependence-related issues between multiple processing units and enable to filter the flexible area on multicore decoder. In addition, we introduce the adaptive deblocking filtering order (ADFO) to minimize the impact of bus congestion when multiple cores interoperate for processing very large data. Furthermore, we design the deblocking filter with skip mode pipelining to achieve the high performance minimizing the increased cost and the power consumption. For SAO, we apply the window-based parallel SAO filtering scheme. The resource sharing is considered throughout the entire architecture. Based on both experimental and analytical results, our proposed design can achieve more than 1.31 Gpixels/s and less than 2.6 Gpixels/s at maximum frequency 660 MHz in single core, and consumes 56.2 Kgates including 10.6 Kgates for memory management architecture, which supports multicore decoder, and about 20.8 mW power on average when synthesizing with the 28 nm CMOS library. Moreover, the skip modes of DF improve both the performance and the power dissipation. The ADFO improves the performance of ∼9.17% when decoding 8 K sequence on octacore at 400 MHz frequency. TpG (Throughput per Gate) is the highest among the related works.

Original languageEnglish
Pages (from-to)810-824
Number of pages15
JournalIEEE Transactions on Multimedia
Issue number4
Publication statusPublished - 2018 Apr

Bibliographical note

Funding Information:
Manuscript received April 12, 2016; accepted August 18, 2017. Date of publication October 5, 2017; date of current version March 15, 2018. This work was supported by the ICT R&D program of MSIP/IITP (2017-0-00261, Intelligent Many-Core Processor and SW based on Low-Power Hypervisor). The associate editor coordinating the review of this manuscript and approving it for publication was Prof. Leonel Sousa. (Corresponding author: JeongGil Ko.) H. Kim and S. Park are with the Department of Computer Software, University of Science and Technology, Daejeon 34113, South Korea, and also with the Intelligent SoC Research Department, Electronics and Telecommunication Research Institute, Daejeon 34129, South Korea (e-mail:;

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Media Technology
  • Computer Science Applications
  • Electrical and Electronic Engineering


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