In recent ATM forum activities, considerable efforts have been focused on an Available Bit Rate (ABR) service, which enables maximal link utilization in the ATM network. In this paper, we present an efficient architecture of an ABR service engine, which includes all functions required in the ABR service algorithm. The new architecture of the ABR service engine is very small in size and high speed by computing the congestion control information without cell delay.
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|Publication status||Published - 2001|
|Event||14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States|
Duration: 2001 Sept 12 → 2001 Sept 15
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering