An effective rasterization architecture for mobile vector graphics processors

Jinhong Park, Jinwoo Kim, Woo Chan Park, Youngsik Kim, Chelho Jeong, Tack Don Han

Research output: Contribution to journalArticlepeer-review


This paper proposed a novel index board rasterization architecture which reduces mathematical calculations and memory traffic for vector graphics. The proposed architecture uses the cell based method which has advantages in computational complexity, and generates the active span by referring to only valid cells and placing them in scanline order with two internal SRAMs. The proposed architecture reduces the amount of calculation by an average of 59.4% and also the external memory traffic by an average of 30.0% compared to the traditional architecture.

Original languageEnglish
Pages (from-to)835-841
Number of pages7
Journalieice electronics express
Issue number11
Publication statusPublished - 2011

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


Dive into the research topics of 'An effective rasterization architecture for mobile vector graphics processors'. Together they form a unique fingerprint.

Cite this