An effective parallel alpg using instruction for high speed memory testing

Hyunjun Yoon; Myung Hoon Yang; Yongjoon Kim; Youngkyu Park; Jaeseok Park; Sungho Kang

doi:10.1109/SOCDC.2008.4815649

An effective parallel alpg using instruction for high speed memory testing

Hyunjun Yoon, Myung Hoon Yang, Yongjoon Kim, Youngkyu Park, Jaeseok Park, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	I370-I375
DOIs	https://doi.org/10.1109/SOCDC.2008.4815649
Publication status	Published - 2008
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 2008 Nov 24 → 2008 Nov 25

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	1

Other

Other	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	08/11/24 → 08/11/25

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software

Access to Document

10.1109/SOCDC.2008.4815649

Cite this

@inproceedings{8ed97ae2612847f89b30527fea857858,

title = "An effective parallel alpg using instruction for high speed memory testing",

abstract = "This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.",

author = "Hyunjun Yoon and Yang, {Myung Hoon} and Yongjoon Kim and Youngkyu Park and Jaeseok Park and Sungho Kang",

year = "2008",

doi = "10.1109/SOCDC.2008.4815649",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "I370--I375",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

}

Yoon, H, Yang, MH, Kim, Y, Park, Y, Park, J & Kang, S 2008, An effective parallel alpg using instruction for high speed memory testing. in 2008 International SoC Design Conference, ISOCC 2008., 4815649, 2008 International SoC Design Conference, ISOCC 2008, vol. 1, pp. I370-I375, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 08/11/24. https://doi.org/10.1109/SOCDC.2008.4815649

TY - GEN

T1 - An effective parallel alpg using instruction for high speed memory testing

AU - Yoon, Hyunjun

AU - Yang, Myung Hoon

AU - Kim, Yongjoon

AU - Park, Youngkyu

AU - Park, Jaeseok

AU - Kang, Sungho

PY - 2008

Y1 - 2008

N2 - This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.

AB - This paper presents the design and implementation of a new parallel Algorithmic Pattern Generator (ALPG) of Automatic Test Equipment (ATE) for the high speed memory testing. We implemented the Instruction Analyzer (IA) that unrolls the instructions using simple instructions. And, unrolled instruction memory is also implemented to reduce the delay of the IA. These implementations allow the ALPG to operate flexible algorithms at high speed. For high speed, we also designed the ALPG of multiple Pattern Generators (PG) with phase-shifting clocks. Therefore, the ALPG has expandability and operates at high speed with the high flexibility of the algorithms.

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M3 - Conference contribution

AN - SCOPUS:69949099055

SN - 9781424425990

T3 - 2008 International SoC Design Conference, ISOCC 2008

SP - I370-I375

BT - 2008 International SoC Design Conference, ISOCC 2008

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -

An effective parallel alpg using instruction for high speed memory testing

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