An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

Mei Ying Bian; Su Kyung Yoon; Shin Dug Kim

doi:10.1007/978-94-007-5860-5_148

An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

Mei Ying Bian, Su Kyung Yoon, Shin Dug Kim

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.

Original language	English
Title of host publication	IT Convergence and Security 2012
Pages	1237-1242
Number of pages	6
DOIs	https://doi.org/10.1007/978-94-007-5860-5_148
Publication status	Published - 2013
Event	International Conference on IT Convergence and Security, ICITCS 2012 - Pyeong Chang, Korea, Republic of Duration: 2012 Dec 5 → 2012 Dec 7

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	215 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Other

Other	International Conference on IT Convergence and Security, ICITCS 2012
Country/Territory	Korea, Republic of
City	Pyeong Chang
Period	12/12/5 → 12/12/7

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1007/978-94-007-5860-5_148

Cite this

@inproceedings{3a57e4b01c79479495b01951d2b42bea,

title = "An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer",

abstract = "An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.",

keywords = "Buffer management, Memory hierarchy, PRAM",

author = "Bian, {Mei Ying} and Yoon, {Su Kyung} and Kim, {Shin Dug}",

year = "2013",

doi = "10.1007/978-94-007-5860-5_148",

language = "English",

isbn = "9789400758599",

series = "Lecture Notes in Electrical Engineering",

pages = "1237--1242",

booktitle = "IT Convergence and Security 2012",

note = "International Conference on IT Convergence and Security, ICITCS 2012 ; Conference date: 05-12-2012 Through 07-12-2012",

}

Bian, MY, Yoon, SK & Kim, SD 2013, An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer. in IT Convergence and Security 2012. Lecture Notes in Electrical Engineering, vol. 215 LNEE, pp. 1237-1242, International Conference on IT Convergence and Security, ICITCS 2012, Pyeong Chang, Korea, Republic of, 12/12/5. https://doi.org/10.1007/978-94-007-5860-5_148

TY - GEN

T1 - An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

AU - Bian, Mei Ying

AU - Yoon, Su Kyung

AU - Kim, Shin Dug

PY - 2013

Y1 - 2013

N2 - An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.

AB - An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.

KW - Buffer management

KW - Memory hierarchy

KW - PRAM

UR - http://www.scopus.com/inward/record.url?scp=84874136014&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874136014&partnerID=8YFLogxK

U2 - 10.1007/978-94-007-5860-5_148

DO - 10.1007/978-94-007-5860-5_148

M3 - Conference contribution

AN - SCOPUS:84874136014

SN - 9789400758599

T3 - Lecture Notes in Electrical Engineering

SP - 1237

EP - 1242

BT - IT Convergence and Security 2012

T2 - International Conference on IT Convergence and Security, ICITCS 2012

Y2 - 5 December 2012 through 7 December 2012

ER -

An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

Abstract

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UN SDGs

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