An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

J. H. Lee; G. H. Park; Shin Dug Kim

doi:10.1109/EMPDP.2003.1183574

An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

J. H. Lee, G. H. Park, Shin Dug Kim

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% ∼ 60% lower than these various cache systems.

Original language	English
Title of host publication	Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003
Editors	Andrea Clematis
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	109-116
Number of pages	8
ISBN (Electronic)	0769518753, 9780769518756
DOIs	https://doi.org/10.1109/EMPDP.2003.1183574
Publication status	Published - 2003
Event	11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003 - Genova, Italy Duration: 2003 Feb 5 → 2003 Feb 7

Publication series

Name	Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003

Other

Other	11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003
Country/Territory	Italy
City	Genova
Period	03/2/5 → 03/2/7

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computational Theory and Mathematics
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/EMPDP.2003.1183574

Cite this

Lee, J. H., Park, G. H., & Kim, S. D. (2003). An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications. In A. Clematis (Ed.), Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003 (pp. 109-116). Article 1183574 (Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMPDP.2003.1183574

Lee, J. H. ; Park, G. H. ; Kim, Shin Dug. / An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications. Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003. editor / Andrea Clematis. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 109-116 (Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003).

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title = "An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications",

abstract = "This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% ∼ 60% lower than these various cache systems.",

author = "Lee, {J. H.} and Park, {G. H.} and Kim, {Shin Dug}",

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year = "2003",

doi = "10.1109/EMPDP.2003.1183574",

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Lee, JH, Park, GH & Kim, SD 2003, An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications. in A Clematis (ed.), Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003., 1183574, Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003, Institute of Electrical and Electronics Engineers Inc., pp. 109-116, 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003, Genova, Italy, 03/2/5. https://doi.org/10.1109/EMPDP.2003.1183574

An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications. / Lee, J. H.; Park, G. H.; Kim, Shin Dug.
Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003. ed. / Andrea Clematis. Institute of Electrical and Electronics Engineers Inc., 2003. p. 109-116 1183574 (Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% ∼ 60% lower than these various cache systems.

AB - This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% ∼ 60% lower than these various cache systems.

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Lee JH, Park GH, Kim SD. An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications. In Clematis A, editor, Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 109-116. 1183574. (Proceedings - 11th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Euro-PDP 2003). doi: 10.1109/EMPDP.2003.1183574

An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

Abstract

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