TY - GEN
T1 - An accurate and energy-efficient way determination technique for instruction caches by using early tag matching
AU - Chung, Eui Young
AU - Kim, Cheol Hong
AU - Chung, Sung Woo
PY - 2008
Y1 - 2008
N2 - This paper proposes an accurate and energy-efficient way determination (instead of prediction) technique for reducing energy consumption in the instruction cache by using early tag matching. Way prediction has been considered as one of the most efficient techniques to reduce energy consumption in the caches. The proposed scheme allows early tag matching for accurate way determination. With this feature, our scheme drastically improves the way determination accuracy compared to the previous way prediction techniques. To enable the early tag matching, the tag lookup stage is inserted prior to the fetch stage in the pipeline architecture. The tag matching is performed during the tag lookup stage, and then only one way is accessed during the fetch stage, leading to good energy efficiency. Simulation results show that the proposed technique reduces the energy consumption in the instruction cache by 55.1% on average. Moreover, our technique guarantees negligible performance degradation by overlapping two pipeline stages in case of branch misprediction.
AB - This paper proposes an accurate and energy-efficient way determination (instead of prediction) technique for reducing energy consumption in the instruction cache by using early tag matching. Way prediction has been considered as one of the most efficient techniques to reduce energy consumption in the caches. The proposed scheme allows early tag matching for accurate way determination. With this feature, our scheme drastically improves the way determination accuracy compared to the previous way prediction techniques. To enable the early tag matching, the tag lookup stage is inserted prior to the fetch stage in the pipeline architecture. The tag matching is performed during the tag lookup stage, and then only one way is accessed during the fetch stage, leading to good energy efficiency. Simulation results show that the proposed technique reduces the energy consumption in the instruction cache by 55.1% on average. Moreover, our technique guarantees negligible performance degradation by overlapping two pipeline stages in case of branch misprediction.
UR - http://www.scopus.com/inward/record.url?scp=50649118104&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50649118104&partnerID=8YFLogxK
U2 - 10.1109/DELTA.2008.57
DO - 10.1109/DELTA.2008.57
M3 - Conference contribution
AN - SCOPUS:50649118104
SN - 0769531105
SN - 9780769531106
T3 - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
SP - 190
EP - 195
BT - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
T2 - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Y2 - 23 January 2008 through 25 January 2008
ER -