An 8Gb multi-level NAND flash memory in a 63nm CMOS process

Dae Seok Byeon, Sung Soo Lee, Young Ho Lim, Jin Sung Park, Wook Kee Han, Pan Suk Kwak, Dong Hwan Kim, Dong Hyuk Chae, Seung Hyun Moon, Seung Jae Lee, Hyun Chul Cho, Jung Woo Lee, Moo Sung Kim, Joon Sung Yang, Young Woo Park, Duk Won Bae, Jung Dal Choi, Sung Hoi Hur, Kang Deog Suh

Research output: Contribution to journalConference articlepeer-review


An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm2 and 133mm2, respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.

Original languageEnglish
Article number2.2
Pages (from-to)22-23+499
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2005
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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