An 8Gb multi-level NAND flash memory in a 63nm CMOS process

Dae Seok Byeon; Sung Soo Lee; Young Ho Lim; Jin Sung Park; Wook Kee Han; Pan Suk Kwak; Dong Hwan Kim; Dong Hyuk Chae; Seung Hyun Moon; Seung Jae Lee; Hyun Chul Cho; Jung Woo Lee; Moo Sung Kim; Joon Sung Yang; Young Woo Park; Duk Won Bae; Jung Dal Choi; Sung Hoi Hur; Kang Deog Suh

An 8Gb multi-level NAND flash memory in a 63nm CMOS process

Dae Seok Byeon, Sung Soo Lee, Young Ho Lim, Jin Sung Park, Wook Kee Han, Pan Suk Kwak, Dong Hwan Kim, Dong Hyuk Chae, Seung Hyun Moon, Seung Jae Lee, Hyun Chul Cho, Jung Woo Lee, Moo Sung Kim, Joon Sung Yang, Young Woo Park, Duk Won Bae, Jung Dal Choi, Sung Hoi Hur, Kang Deog Suh

College of Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm² and 133mm², respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.

Original language	English
Article number	2.2
Pages (from-to)	22-23+499
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Byeon, D. S., Lee, S. S., Lim, Y. H., Park, J. S., Han, W. K., Kwak, P. S., Kim, D. H., Chae, D. H., Moon, S. H., Lee, S. J., Cho, H. C., Lee, J. W., Kim, M. S., Yang, J. S., Park, Y. W., Bae, D. W., Choi, J. D., Hur, S. H., & Suh, K. D. (2005). An 8Gb multi-level NAND flash memory in a 63nm CMOS process. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 48, 22-23+499. [2.2].

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title = "An 8Gb multi-level NAND flash memory in a 63nm CMOS process",

abstract = "An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm2 and 133mm2, respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.",

author = "Byeon, {Dae Seok} and Lee, {Sung Soo} and Lim, {Young Ho} and Park, {Jin Sung} and Han, {Wook Kee} and Kwak, {Pan Suk} and Kim, {Dong Hwan} and Chae, {Dong Hyuk} and Moon, {Seung Hyun} and Lee, {Seung Jae} and Cho, {Hyun Chul} and Lee, {Jung Woo} and Kim, {Moo Sung} and Yang, {Joon Sung} and Park, {Young Woo} and Bae, {Duk Won} and Choi, {Jung Dal} and Hur, {Sung Hoi} and Suh, {Kang Deog}",

year = "2005",

language = "English",

volume = "48",

pages = "22--23+499",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2005 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

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TY - JOUR

T1 - An 8Gb multi-level NAND flash memory in a 63nm CMOS process

AU - Byeon, Dae Seok

AU - Lee, Sung Soo

AU - Lim, Young Ho

AU - Park, Jin Sung

AU - Han, Wook Kee

AU - Kwak, Pan Suk

AU - Kim, Dong Hwan

AU - Chae, Dong Hyuk

AU - Moon, Seung Hyun

AU - Lee, Seung Jae

AU - Cho, Hyun Chul

AU - Lee, Jung Woo

AU - Kim, Moo Sung

AU - Yang, Joon Sung

AU - Park, Young Woo

AU - Bae, Duk Won

AU - Choi, Jung Dal

AU - Hur, Sung Hoi

AU - Suh, Kang Deog

PY - 2005

Y1 - 2005

N2 - An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm2 and 133mm2, respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.

AB - An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm2 and 133mm2, respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.

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M3 - Conference article

AN - SCOPUS:28144439695

SN - 0193-6530

VL - 48

SP - 22-23+499

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 2.2

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

An 8Gb multi-level NAND flash memory in a 63nm CMOS process

Abstract

All Science Journal Classification (ASJC) codes

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