An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm².