TY - GEN
T1 - All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate
AU - Ryu, Kyungho
AU - Jung, Dong Hoon
AU - Jung, Seong Ook
PY - 2013
Y1 - 2013
N2 - We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
AB - We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
UR - http://www.scopus.com/inward/record.url?scp=84891098921&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84891098921&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2013.6649067
DO - 10.1109/ESSCIRC.2013.6649067
M3 - Conference contribution
AN - SCOPUS:84891098921
SN - 9781479906437
T3 - European Solid-State Circuits Conference
SP - 41
EP - 44
BT - ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference
T2 - 39th European Solid-State Circuits Conference, ESSCIRC 2013
Y2 - 16 September 2013 through 20 September 2013
ER -