All-digital 90°phase-shift DLL with a dithering jitter suppression scheme

Dong Hoon Jung; Kyungho Ryu; Jung Hyun Park; Won Lee; Seong Ook Jung

doi:10.1109/CICC.2013.6658534

All-digital 90°phase-shift DLL with a dithering jitter suppression scheme

Dong Hoon Jung, Kyungho Ryu, Jung Hyun Park, Won Lee, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

Original language	English
Title of host publication	Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781467361460
DOIs	https://doi.org/10.1109/CICC.2013.6658534
Publication status	Published - 2013 Nov 7
Event	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States Duration: 2013 Sept 22 → 2013 Sept 25

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
Country/Territory	United States
City	San Jose, CA
Period	13/9/22 → 13/9/25

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2013.6658534

Cite this

Jung, D. H., Ryu, K., Park, J. H., Lee, W., & Jung, S. O. (2013). All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 Article 6658534 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658534

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title = "All-digital 90°phase-shift DLL with a dithering jitter suppression scheme",

abstract = "We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.",

author = "Jung, {Dong Hoon} and Kyungho Ryu and Park, {Jung Hyun} and Won Lee and Jung, {Seong Ook}",

year = "2013",

month = nov,

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doi = "10.1109/CICC.2013.6658534",

language = "English",

isbn = "9781467361460",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",

address = "United States",

note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",

}

Jung, DH, Ryu, K, Park, JH, Lee, W & Jung, SO 2013, All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013., 6658534, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, United States, 13/9/22. https://doi.org/10.1109/CICC.2013.6658534

All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. / Jung, Dong Hoon; Ryu, Kyungho; Park, Jung Hyun et al.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6658534 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Jung, Dong Hoon

AU - Ryu, Kyungho

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N2 - We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

AB - We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

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ER -

All-digital 90°phase-shift DLL with a dithering jitter suppression scheme

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