ADDLL for clock-deskew buffer in high-performance SoCs

Jung Hyun Park, Dong Hoon Jung, Kyungho Ryu, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


In this brief, we propose an all-digital delay locked loop (ADDLL) for a clock-deskew buffer. A low static phase offset at a high operating frequency is achieved by adopting a high-resolution window phase detector (PD) and a tristate-inverter-based ladder type coarse delay line (CDL). The proposed PD generates a high-resolution detection window that is adaptive to the process-voltage-temperature variation and reduces the static phase offset to nearly half of the fine delay line (FDL) resolution using a dual-output FDL. A proposed CDL is adopted in order to attain a small coarse delay step using tristate-inverters. The proposed ADDLL is designed using 0.13-\μ m process technology with a supply voltage of 1.2 V. The operating frequency range is 700 MHz to 2.0 GHz. The maximum static phase offset is less than 14.75 ps at all conditions and the power consumption is 4.0 mW at 2.0 GHz.

Original languageEnglish
Article number6289379
Pages (from-to)1368-1373
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
Publication statusPublished - 2013

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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