TY - GEN
T1 - Adaptive detection and concealment algorithm of defective pixel
AU - Jeehoon, An
AU - Wonjae, Lee
AU - Jaeseok, Kim
PY - 2007
Y1 - 2007
N2 - This paper proposes a defective pixel detection algorithm for CCD/CMOS image sensors and its hardware architecture. In previous algorithms, the characteristics of images have not been considered and normal pixels can be treated as defective pixels with high possibility. In order to make up for those disadvantages, the proposed algorithm detects defective pixels by considering the characteristics of the image and verifies them using several frames while checking scene-changes. Whenever a scene-change is occurred, potentially defective pixels are detected and verified. The proposed algorithm was implemented with Verilog HDL. Total logic gate count was 5.1k using 0.25um CMOS standard cell library.
AB - This paper proposes a defective pixel detection algorithm for CCD/CMOS image sensors and its hardware architecture. In previous algorithms, the characteristics of images have not been considered and normal pixels can be treated as defective pixels with high possibility. In order to make up for those disadvantages, the proposed algorithm detects defective pixels by considering the characteristics of the image and verifies them using several frames while checking scene-changes. Whenever a scene-change is occurred, potentially defective pixels are detected and verified. The proposed algorithm was implemented with Verilog HDL. Total logic gate count was 5.1k using 0.25um CMOS standard cell library.
UR - http://www.scopus.com/inward/record.url?scp=47949089521&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47949089521&partnerID=8YFLogxK
U2 - 10.1109/SIPS.2007.4387626
DO - 10.1109/SIPS.2007.4387626
M3 - Conference contribution
AN - SCOPUS:47949089521
SN - 1424412226
SN - 9781424412228
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 651
EP - 656
BT - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
T2 - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Y2 - 17 October 2007 through 19 October 2007
ER -