Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors with CMOS-Friendly Approaches

Two-dimensional (2D) transition metal dichalco-genides (TMDs) are promising for future nanoscale transistors, but reducing their gate dielectric equivalent oxide thickness (EOT) remains a key challenge. Here, we report ultrathin top-gate dielectrics on monolayer (1L) TMDs using industry-com-patible approaches, achieving 1-nm-scale EOT. We show atomic layer deposition (ALD) of HfO₂ on both 1L Mos2 and WSe₂ using Si seed, realizing 0.9 nm EOT with subthreshold swing SS≈ 70 mV/dec, low leakage, and negligible hysteresis on Mos2. We also demonstrate direct ALD of ultrathin alumina (AlO_x) on 1L Mos2 with good uniformity and quality by engi-neering the precursor. Combining our findings, we show that the threshold voltage (V_T) can be controlled by the thickness of the interfacial dielectric layer on the 2D transistor channel.