A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

Mei Ying Bian, Su Kyung Yoon, Jeong Geun Kim, Sangjae Nam, Shin Dug Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

Original languageEnglish
Pages (from-to)137-146
Number of pages10
JournalJournal of Computer Science and Technology
Issue number1
Publication statusPublished - 2016 Jan 1

Bibliographical note

Funding Information:
This work was supported by an Industry-Academy Joint Research program between Samsung Electronics and Yonsei University.

Publisher Copyright:
© 2016, Springer Science+Business Media New York.

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics


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