A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs

Young Woo Lee; Junghwan Kim; Inhyuk Choi; Sungho Kang

doi:10.1109/ISOCC.2016.7799724

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs

Young Woo Lee, Junghwan Kim, Inhyuk Choi, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

After the 3D stacking process, TSV-based 3D-ICs are required to perform the post-bond testing in order to detect TSV faults or device functional defects. To detect the resistive open and bridge defects, various effective TSV testing techniques have been studied. At an early stage of TSV manufacturing, it is important to consider that the TSV testing is required not only determining whether each TSV is defective or non-defective, but also digitizing the fault degree into the TSV resistance value during the silicon debugging. In this paper, we propose a new TSV test structure for simultaneously detecting the resistive open and bridge defects with supporting the debug mode to analysis the characteristic of the specific TSV. It can highly reduce the test time by detecting TSV defects at the same time without compromising test quality.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	129-130
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799724
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799724

Cite this

Lee, Y. W., Kim, J., Choi, I., & Kang, S. (2016). A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 129-130). Article 7799724 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799724

Lee, Young Woo ; Kim, Junghwan ; Choi, Inhyuk et al. / A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 129-130 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

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title = "A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs",

abstract = "After the 3D stacking process, TSV-based 3D-ICs are required to perform the post-bond testing in order to detect TSV faults or device functional defects. To detect the resistive open and bridge defects, various effective TSV testing techniques have been studied. At an early stage of TSV manufacturing, it is important to consider that the TSV testing is required not only determining whether each TSV is defective or non-defective, but also digitizing the fault degree into the TSV resistance value during the silicon debugging. In this paper, we propose a new TSV test structure for simultaneously detecting the resistive open and bridge defects with supporting the debug mode to analysis the characteristic of the specific TSV. It can highly reduce the test time by detecting TSV defects at the same time without compromising test quality.",

author = "Lee, {Young Woo} and Junghwan Kim and Inhyuk Choi and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

year = "2016",

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doi = "10.1109/ISOCC.2016.7799724",

language = "English",

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Lee, YW, Kim, J, Choi, I & Kang, S 2016, A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799724, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 129-130, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799724

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. / Lee, Young Woo; Kim, Junghwan; Choi, Inhyuk et al.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 129-130 7799724 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Lee YW, Kim J, Choi I, Kang S. A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 129-130. 7799724. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799724

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs

Abstract

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