A Time-Interleaved Recursive Loop Band-Pass Delta-Sigma Modulator for a Digital IF CDMA Receiver

Minho Kwon; Gunhee Han; Jungyoon Lee

doi:10.1109/TCSII.2005.850424

A Time-Interleaved Recursive Loop Band-Pass Delta-Sigma Modulator for a Digital IF CDMA Receiver

Minho Kwon, Gunhee Han, Jungyoon Lee

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm².

Original language	English
Pages (from-to)	389-393
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	52
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2005.850424
Publication status	Published - 2005 Jul 5

Bibliographical note

Funding Information:
Manuscript received October 6, 2003; revised April 15, 2004. This work was supported in part by the Ministry of Information & Communications, Korea, under the Information Technology Research Center Support Program. This paper was recommended by Associate Editor U. Moon.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2005.850424

Cite this

@article{f25d56465c6649348cb2497c24198a9c,

title = "A Time-Interleaved Recursive Loop Band-Pass Delta-Sigma Modulator for a Digital IF CDMA Receiver",

abstract = "A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.",

author = "Minho Kwon and Gunhee Han and Jungyoon Lee",

note = "Funding Information: Manuscript received October 6, 2003; revised April 15, 2004. This work was supported in part by the Ministry of Information & Communications, Korea, under the Information Technology Research Center Support Program. This paper was recommended by Associate Editor U. Moon.",

year = "2005",

month = jul,

day = "5",

doi = "10.1109/TCSII.2005.850424",

language = "English",

volume = "52",

pages = "389--393",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - A Time-Interleaved Recursive Loop Band-Pass Delta-Sigma Modulator for a Digital IF CDMA Receiver

AU - Kwon, Minho

AU - Han, Gunhee

AU - Lee, Jungyoon

N1 - Funding Information: Manuscript received October 6, 2003; revised April 15, 2004. This work was supported in part by the Ministry of Information & Communications, Korea, under the Information Technology Research Center Support Program. This paper was recommended by Associate Editor U. Moon.

PY - 2005/7/5

Y1 - 2005/7/5

N2 - A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

AB - A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

UR - http://www.scopus.com/inward/record.url?scp=24044537867&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=24044537867&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2005.850424

DO - 10.1109/TCSII.2005.850424

M3 - Article

AN - SCOPUS:24044537867

SN - 1549-7747

VL - 52

SP - 389

EP - 393

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 7

ER -

A Time-Interleaved Recursive Loop Band-Pass Delta-Sigma Modulator for a Digital IF CDMA Receiver

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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