A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications

Sekeon Kim; Keonhee Cho; Kyeongrim Baek; Hyunjun Kim; Younmee Bae; Mijung Kim; Dongwook Seo; Sangyeop Baeck; Sungjae Lee; Seong Ook Jung

doi:10.23919/VLSITechnologyandCir57934.2023.10185239

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications

Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a dual-edge-triggered flip-flop (DET-FF) with redundant internal node transition elimination (RTEDET) to achieve minimal dynamic power consumption. The proposed RTEDET shows lower total power by 37%/39% than the recent low-power flip-flop/conventional DET-FF thanks to the halved CK frequency and the redundant internal node transition elimination. In addition, the proposed RTEDET can operate at supply voltage down to 0.35V in all chips with its static operation and contention-free feature.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185239
Publication status	Published - 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 2023 Jun 11 → 2023 Jun 16

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	23/6/11 → 23/6/16

Bibliographical note

Publisher Copyright:
© 2023 JSAP.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185239

Cite this

Kim, S., Cho, K., Baek, K., Kim, H., Bae, Y., Kim, M., Seo, D., Baeck, S., Lee, S., & Jung, S. O. (2023). A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185239

Kim, Sekeon ; Cho, Keonhee ; Baek, Kyeongrim et al. / A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications",

abstract = "This paper presents a dual-edge-triggered flip-flop (DET-FF) with redundant internal node transition elimination (RTEDET) to achieve minimal dynamic power consumption. The proposed RTEDET shows lower total power by 37%/39% than the recent low-power flip-flop/conventional DET-FF thanks to the halved CK frequency and the redundant internal node transition elimination. In addition, the proposed RTEDET can operate at supply voltage down to 0.35V in all chips with its static operation and contention-free feature.",

author = "Sekeon Kim and Keonhee Cho and Kyeongrim Baek and Hyunjun Kim and Younmee Bae and Mijung Kim and Dongwook Seo and Sangyeop Baeck and Sungjae Lee and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185239",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

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Kim, S, Cho, K, Baek, K, Kim, H, Bae, Y, Kim, M, Seo, D, Baeck, S, Lee, S & Jung, SO 2023, A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 23/6/11. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185239

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. / Kim, Sekeon; Cho, Keonhee; Baek, Kyeongrim et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Sekeon

AU - Cho, Keonhee

AU - Baek, Kyeongrim

AU - Kim, Hyunjun

AU - Bae, Younmee

AU - Kim, Mijung

AU - Seo, Dongwook

AU - Baeck, Sangyeop

AU - Lee, Sungjae

AU - Jung, Seong Ook

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N2 - This paper presents a dual-edge-triggered flip-flop (DET-FF) with redundant internal node transition elimination (RTEDET) to achieve minimal dynamic power consumption. The proposed RTEDET shows lower total power by 37%/39% than the recent low-power flip-flop/conventional DET-FF thanks to the halved CK frequency and the redundant internal node transition elimination. In addition, the proposed RTEDET can operate at supply voltage down to 0.35V in all chips with its static operation and contention-free feature.

AB - This paper presents a dual-edge-triggered flip-flop (DET-FF) with redundant internal node transition elimination (RTEDET) to achieve minimal dynamic power consumption. The proposed RTEDET shows lower total power by 37%/39% than the recent low-power flip-flop/conventional DET-FF thanks to the halved CK frequency and the redundant internal node transition elimination. In addition, the proposed RTEDET can operate at supply voltage down to 0.35V in all chips with its static operation and contention-free feature.

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BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

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Kim S, Cho K, Baek K, Kim H, Bae Y, Kim M et al. A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185239

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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