A spur free 0.4-V 88-μW 200-MHz phase-locked loop

Joung Wook Moon; Kwang Chun Choi; Min Hyeong Kim; Woo Young Choi

doi:10.1109/ISOCC.2013.6864005

A spur free 0.4-V 88-μW 200-MHz phase-locked loop

Joung Wook Moon, Kwang Chun Choi, Min Hyeong Kim, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm² and consumes 88 μW at 0.4-V supply for 200-MHz operation.

Original language	English
Title of host publication	ISOCC 2013 - 2013 International SoC Design Conference
Publisher	IEEE Computer Society
Pages	134-137
Number of pages	4
ISBN (Print)	9781479911417
DOIs	https://doi.org/10.1109/ISOCC.2013.6864005
Publication status	Published - 2013
Event	2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of Duration: 2013 Nov 17 → 2013 Nov 19

Publication series

Name	ISOCC 2013 - 2013 International SoC Design Conference

Other

Other	2013 International SoC Design Conference, ISOCC 2013
Country/Territory	Korea, Republic of
City	Busan
Period	13/11/17 → 13/11/19

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC.2013.6864005

Cite this

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title = "A spur free 0.4-V 88-μW 200-MHz phase-locked loop",

abstract = "An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.",

author = "Moon, {Joung Wook} and Choi, {Kwang Chun} and Kim, {Min Hyeong} and Choi, {Woo Young}",

year = "2013",

doi = "10.1109/ISOCC.2013.6864005",

language = "English",

isbn = "9781479911417",

series = "ISOCC 2013 - 2013 International SoC Design Conference",

publisher = "IEEE Computer Society",

pages = "134--137",

booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",

address = "United States",

note = "2013 International SoC Design Conference, ISOCC 2013 ; Conference date: 17-11-2013 Through 19-11-2013",

}

Moon, JW, Choi, KC, Kim, MH & Choi, WY 2013, A spur free 0.4-V 88-μW 200-MHz phase-locked loop. in ISOCC 2013 - 2013 International SoC Design Conference., 6864005, ISOCC 2013 - 2013 International SoC Design Conference, IEEE Computer Society, pp. 134-137, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6864005

TY - GEN

T1 - A spur free 0.4-V 88-μW 200-MHz phase-locked loop

AU - Moon, Joung Wook

AU - Choi, Kwang Chun

AU - Kim, Min Hyeong

AU - Choi, Woo Young

PY - 2013

Y1 - 2013

N2 - An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

AB - An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

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U2 - 10.1109/ISOCC.2013.6864005

DO - 10.1109/ISOCC.2013.6864005

M3 - Conference contribution

AN - SCOPUS:84906896241

SN - 9781479911417

T3 - ISOCC 2013 - 2013 International SoC Design Conference

SP - 134

EP - 137

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

T2 - 2013 International SoC Design Conference, ISOCC 2013

Y2 - 17 November 2013 through 19 November 2013

ER -

A spur free 0.4-V 88-μW 200-MHz phase-locked loop

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