Abstract
A new method of sidelobe level (SLL) reduction for a substrate integrated waveguide (SIW) slot array antenna is presented. In this method, amplitude distribution is assigned to the slots by tapering the SIW width. The SIW with tapered width can be efficiently manufactured by varying the position of the side-wall vias. In this letter, the new method is verified on a 12-element SIW slot array antenna operating at 94 GHz to achieve SLL around -30 dB. The antenna design procedure as well as simulation and measurement results are presented.
| Original language | English |
|---|---|
| Article number | 8735804 |
| Pages (from-to) | 1557-1561 |
| Number of pages | 5 |
| Journal | IEEE Antennas and Wireless Propagation Letters |
| Volume | 18 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2019 Aug |
Bibliographical note
Funding Information:Manuscript received May 22, 2019; accepted June 4, 2019. Date of publication June 12, 2019; date of current version August 2, 2019. This work was supported in part by the Ministry of Science and ICT (MSIT), South Korea, under the “ICT Consilience Creative Program” (IITP-2019-2017-0-01015) supervised by the Institute for Information and Communications Technology Planning and Evaluation (IITP), and in part by the ICT R&D program (2017-0-00678) of MSIT/IITP. (Corresponding author: Min-Ho Ka.) The authors are with the School of Integrated Technology, Yonsei University, Incheon 406-840, South Korea (e-mail: dewantariaulia@gmail. com; jaeheung@yonsei.ac.kr; igor_scherbatko@yahoo.com; kaminho@yonsei. ac.kr). Digital Object Identifier 10.1109/LAWP.2019.2922307
Funding Information:
This work was supported in part by the Ministry of Science and ICT (MSIT), South Korea, under the ICT Consilience Creative Program (IITP-2019-2017-0-01015)
Publisher Copyright:
© 2002-2011 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering