A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang

doi:10.1109/ISOCC.2017.8368799

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	121-122
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368799
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Bibliographical note

Funding Information:
This work supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2015R1A2A1A13001751)

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368799

Cite this

Oh, H., Kim, H., Lim, J., & Kang, S. (2018). A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 121-122). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368799

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abstract = "In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.",

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Oh, H, Kim, H, Lim, J & Kang, S 2018, A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 121-122, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368799

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. / Oh, Hyunggoy; Kim, Heetae; Lim, Jaeil et al.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 121-122 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Oh H, Kim H, Lim J, Kang S. A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 121-122. (Proceedings - International SoC Design Conference 2017, ISOCC 2017). doi: 10.1109/ISOCC.2017.8368799

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

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