From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems. The large number of scan cells lead to excessive switching activities during the scan shifting operations. In this paper, we present a new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic. This method prevents cumulative transitions caused by shifting operations of the scan cells. In addition, the existing compression schemes can be compatible with the proposed method without modification of decompression architecture. Experimental results on ITC'99 benchmark circuits and industrial circuits show that this shifting method reduces the scan shifting power in all cases. In spite of outperformed power, a burden of the extra logic is not necessary to be contemplated.
|Title of host publication||Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|Publication status||Published - 2015 Apr 13|
|Event||16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States|
Duration: 2015 Mar 2 → 2015 Mar 4
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||16th International Symposium on Quality Electronic Design, ISQED 2015|
|Period||15/3/2 → 15/3/4|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality