A scan shifting method based on clock gating of multiple groups for low power scan testing

Sungyoul Seo; Yong Lee; Joohwan Lee; Sungho Kang

doi:10.1109/ISQED.2015.7085417

A scan shifting method based on clock gating of multiple groups for low power scan testing

Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems. The large number of scan cells lead to excessive switching activities during the scan shifting operations. In this paper, we present a new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic. This method prevents cumulative transitions caused by shifting operations of the scan cells. In addition, the existing compression schemes can be compatible with the proposed method without modification of decompression architecture. Experimental results on ITC'99 benchmark circuits and industrial circuits show that this shifting method reduces the scan shifting power in all cases. In spite of outperformed power, a burden of the extra logic is not necessary to be contemplated.

Original language	English
Title of host publication	Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
Publisher	IEEE Computer Society
Pages	162-166
Number of pages	5
ISBN (Electronic)	9781479975815
DOIs	https://doi.org/10.1109/ISQED.2015.7085417
Publication status	Published - 2015 Apr 13
Event	16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States Duration: 2015 Mar 2 → 2015 Mar 4

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2015-April
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	16th International Symposium on Quality Electronic Design, ISQED 2015
Country/Territory	United States
City	Santa Clara
Period	15/3/2 → 15/3/4

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2015.7085417

Cite this

Seo, S., Lee, Y., Lee, J., & Kang, S. (2015). A scan shifting method based on clock gating of multiple groups for low power scan testing. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (pp. 162-166). Article 7085417 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April). IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085417

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abstract = "From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems. The large number of scan cells lead to excessive switching activities during the scan shifting operations. In this paper, we present a new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic. This method prevents cumulative transitions caused by shifting operations of the scan cells. In addition, the existing compression schemes can be compatible with the proposed method without modification of decompression architecture. Experimental results on ITC'99 benchmark circuits and industrial circuits show that this shifting method reduces the scan shifting power in all cases. In spite of outperformed power, a burden of the extra logic is not necessary to be contemplated.",

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Seo, S, Lee, Y, Lee, J & Kang, S 2015, A scan shifting method based on clock gating of multiple groups for low power scan testing. in Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015., 7085417, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2015-April, IEEE Computer Society, pp. 162-166, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 15/3/2. https://doi.org/10.1109/ISQED.2015.7085417

A scan shifting method based on clock gating of multiple groups for low power scan testing. / Seo, Sungyoul; Lee, Yong; Lee, Joohwan et al.
Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. p. 162-166 7085417 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Seo S, Lee Y, Lee J, Kang S. A scan shifting method based on clock gating of multiple groups for low power scan testing. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society. 2015. p. 162-166. 7085417. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2015.7085417

A scan shifting method based on clock gating of multiple groups for low power scan testing

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