A RAM cache approach using host memory buffer of the NVMe interface

Ju Hyung Hong, Sang Woo Han, Eui Young Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


This paper proposes new methods with Host Memory Buffer to improve IO performance in NVMe interface. Although Host Memory Buffer is a versatile memory architecture, it has been considered limitedly as metadata cache such as Logical-To- Physical table. The proposed architecture uses Host Memory Buffer as data cache with modification of an NVMe command process and the additional DMA path between system memory and Host Memory Buffer. The proposed architecture improves the performance of IO request by 23% in case of sequential writes compared to a device buffer architecture.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things


Other13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation


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