A RAM cache approach using host memory buffer of the NVMe interface

Ju Hyung Hong; Sang Woo Han; Eui Young Chung

doi:10.1109/ISOCC.2016.7799757

A RAM cache approach using host memory buffer of the NVMe interface

Ju Hyung Hong, Sang Woo Han, Eui Young Chung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper proposes new methods with Host Memory Buffer to improve IO performance in NVMe interface. Although Host Memory Buffer is a versatile memory architecture, it has been considered limitedly as metadata cache such as Logical-To- Physical table. The proposed architecture uses Host Memory Buffer as data cache with modification of an NVMe command process and the additional DMA path between system memory and Host Memory Buffer. The proposed architecture improves the performance of IO request by 23% in case of sequential writes compared to a device buffer architecture.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	109-110
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799757
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799757

Cite this

Hong, J. H., Han, S. W., & Chung, E. Y. (2016). A RAM cache approach using host memory buffer of the NVMe interface. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 109-110). [7799757] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799757

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abstract = "This paper proposes new methods with Host Memory Buffer to improve IO performance in NVMe interface. Although Host Memory Buffer is a versatile memory architecture, it has been considered limitedly as metadata cache such as Logical-To- Physical table. The proposed architecture uses Host Memory Buffer as data cache with modification of an NVMe command process and the additional DMA path between system memory and Host Memory Buffer. The proposed architecture improves the performance of IO request by 23% in case of sequential writes compared to a device buffer architecture.",

author = "Hong, {Ju Hyung} and Han, {Sang Woo} and Chung, {Eui Young}",

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doi = "10.1109/ISOCC.2016.7799757",

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Hong, JH, Han, SW & Chung, EY 2016, A RAM cache approach using host memory buffer of the NVMe interface. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799757, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 109-110, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799757

A RAM cache approach using host memory buffer of the NVMe interface. / Hong, Ju Hyung; Han, Sang Woo; Chung, Eui Young.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 109-110 7799757 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper proposes new methods with Host Memory Buffer to improve IO performance in NVMe interface. Although Host Memory Buffer is a versatile memory architecture, it has been considered limitedly as metadata cache such as Logical-To- Physical table. The proposed architecture uses Host Memory Buffer as data cache with modification of an NVMe command process and the additional DMA path between system memory and Host Memory Buffer. The proposed architecture improves the performance of IO request by 23% in case of sequential writes compared to a device buffer architecture.

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Hong JH, Han SW, Chung EY. A RAM cache approach using host memory buffer of the NVMe interface. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 109-110. 7799757. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799757

A RAM cache approach using host memory buffer of the NVMe interface

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