A prevenient voltage stress test method for high density memory

Jongsoo Yim; Gunbae Kim; Incheol Nam; Sangki Son; Jonghyoung Lim; Hwacheol Lee; Sangseok Kang; Byungheon Kwak; Jinseok Lee; Sungho Kang

doi:10.1109/DELTA.2008.93

A prevenient voltage stress test method for high density memory

Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

Original language	English
Title of host publication	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages	516-520
Number of pages	5
DOIs	https://doi.org/10.1109/DELTA.2008.93
Publication status	Published - 2008
Event	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong Duration: 2008 Jan 23 → 2008 Jan 25

Publication series

Name	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Other

Other	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Country/Territory	Hong Kong
City	Hong Kong, SAR
Period	08/1/23 → 08/1/25

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/DELTA.2008.93

Cite this

Yim, J., Kim, G., Nam, I., Son, S., Lim, J., Lee, H., Kang, S., Kwak, B., Lee, J., & Kang, S. (2008). A prevenient voltage stress test method for high density memory. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 516-520). Article 4459605 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). https://doi.org/10.1109/DELTA.2008.93

@inproceedings{3e65c65f84e640c5a873feb115bf15a0,

title = "A prevenient voltage stress test method for high density memory",

abstract = "The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).",

author = "Jongsoo Yim and Gunbae Kim and Incheol Nam and Sangki Son and Jonghyoung Lim and Hwacheol Lee and Sangseok Kang and Byungheon Kwak and Jinseok Lee and Sungho Kang",

year = "2008",

doi = "10.1109/DELTA.2008.93",

language = "English",

isbn = "0769531105",

series = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

pages = "516--520",

booktitle = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

note = "4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 ; Conference date: 23-01-2008 Through 25-01-2008",

}

Yim, J, Kim, G, Nam, I, Son, S, Lim, J, Lee, H, Kang, S, Kwak, B, Lee, J & Kang, S 2008, A prevenient voltage stress test method for high density memory. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459605, Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, pp. 516-520, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 08/1/23. https://doi.org/10.1109/DELTA.2008.93

A prevenient voltage stress test method for high density memory. / Yim, Jongsoo; Kim, Gunbae; Nam, Incheol et al.
Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 516-520 4459605 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A prevenient voltage stress test method for high density memory

AU - Yim, Jongsoo

AU - Kim, Gunbae

AU - Nam, Incheol

AU - Son, Sangki

AU - Lim, Jonghyoung

AU - Lee, Hwacheol

AU - Kang, Sangseok

AU - Kwak, Byungheon

AU - Lee, Jinseok

AU - Kang, Sungho

PY - 2008

Y1 - 2008

N2 - The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

AB - The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

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M3 - Conference contribution

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SN - 0769531105

SN - 9780769531106

T3 - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

SP - 516

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BT - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

T2 - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Y2 - 23 January 2008 through 25 January 2008

ER -

Yim J, Kim G, Nam I, Son S, Lim J, Lee H et al. A prevenient voltage stress test method for high density memory. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 516-520. 4459605. (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). doi: 10.1109/DELTA.2008.93

A prevenient voltage stress test method for high density memory

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