A dual data cache system structure, called a cooperative cache system, is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). These two caches are con- structed with different block sizes as well as associativities. The block size of the TOC is 8bytes and that of the SOC is 32bytes, and the capacity of each cache is 8Kbytes. The cooperative cache system achieves improvement in performance and reduces power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that is going to be manufactured by Samsung Electronics Co. with 0.25m technology.
|Title of host publication||Languages, Compilers and Tools for Embedded Systems - ACM SIGPLAN Workshop LCTES 2000, Proceedings|
|Editors||Jack Davidson, Sang Lyul Min|
|Number of pages||16|
|ISBN (Print)||3540417818, 9783540417811|
|Publication status||Published - 2001|
|Event||ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000 - Vancouver, Canada|
Duration: 2000 Jun 18 → 2000 Jun 18
|Name||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|
|Other||ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000|
|Period||00/6/18 → 00/6/18|
Bibliographical notePublisher Copyright:
© Springer-Verlag Berlin Heidelberg 2001.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)