Abstract
This paper introduces a subthreshold voltage reference consisting of two stages: the line sensitivity (LS) stage and the temperature coefficient (TC) stage. In the modified LS stage low-power voltage reference, the native transistor has been replaced with a gate-source connected NMOS. This modification results in process, voltage, and temperature (PVT) variation insensitivity while satisfying the desired pico-watt power consumption. To further enhance the LS, the two stages are configured with a source follower, resulting in a more stable transmission of the output voltage from the first stage to the second stage through the buffer. Additionally, the TC stage compensates for the TC of the Vref using the body effect. Simulated in a standard 180-nm CMOS process, the proposed circuit operates within a supply voltage range of 0.8 V to 1.8 V and generates 338 mV at room temperature. The circuit achieves a TC of 156 ppm/C in the temperature range of -20°C to 100°C, and LS of 0.046%/V. Furthermore, it exhibits a low power consumption of 26.7 pW at 25°C.
Original language | English |
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Title of host publication | Proceedings - International SoC Design Conference 2023, ISOCC 2023 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 45-46 |
Number of pages | 2 |
ISBN (Electronic) | 9798350327038 |
DOIs | |
Publication status | Published - 2023 |
Event | 20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 2023 Oct 25 → 2023 Oct 28 |
Publication series
Name | Proceedings - International SoC Design Conference 2023, ISOCC 2023 |
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Conference
Conference | 20th International SoC Design Conference, ISOCC 2023 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 23/10/25 → 23/10/28 |
Bibliographical note
Publisher Copyright:© 2023 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation