A novel charge pump PLL with reduced jitter characteristics

Myoung Su Lee; Tae Sik Cheung; Woo Young Choi

doi:10.1109/ICVC.1999.821010

A novel charge pump PLL with reduced jitter characteristics

Myoung Su Lee, Tae Sik Cheung, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation.

Original language	English
Title of host publication	ICVC 1999 - 6th International Conference on VLSI and CAD
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	596-598
Number of pages	3
ISBN (Print)	0780357272, 9780780357273
DOIs	https://doi.org/10.1109/ICVC.1999.821010
Publication status	Published - 1999
Event	6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of Duration: 1999 Oct 26 → 1999 Oct 27

Publication series

Name	ICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other	6th International Conference on VLSI and CAD, ICVC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/10/26 → 99/10/27

Bibliographical note

Publisher Copyright:
© 1999 IEEE.

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICVC.1999.821010

Cite this

@inproceedings{eee43d38d1a14da4b20d391e56cc0c5d,

title = "A novel charge pump PLL with reduced jitter characteristics",

abstract = "A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation.",

author = "Lee, {Myoung Su} and Cheung, {Tae Sik} and Choi, {Woo Young}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 6th International Conference on VLSI and CAD, ICVC 1999 ; Conference date: 26-10-1999 Through 27-10-1999",

year = "1999",

doi = "10.1109/ICVC.1999.821010",

language = "English",

isbn = "0780357272",

series = "ICVC 1999 - 6th International Conference on VLSI and CAD",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "596--598",

booktitle = "ICVC 1999 - 6th International Conference on VLSI and CAD",

address = "United States",

}

Lee, MS, Cheung, TS & Choi, WY 1999, A novel charge pump PLL with reduced jitter characteristics. in ICVC 1999 - 6th International Conference on VLSI and CAD., 821010, ICVC 1999 - 6th International Conference on VLSI and CAD, Institute of Electrical and Electronics Engineers Inc., pp. 596-598, 6th International Conference on VLSI and CAD, ICVC 1999, Seoul, Korea, Republic of, 99/10/26. https://doi.org/10.1109/ICVC.1999.821010

A novel charge pump PLL with reduced jitter characteristics. / Lee, Myoung Su; Cheung, Tae Sik; Choi, Woo Young.
ICVC 1999 - 6th International Conference on VLSI and CAD. Institute of Electrical and Electronics Engineers Inc., 1999. p. 596-598 821010 (ICVC 1999 - 6th International Conference on VLSI and CAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A novel charge pump PLL with reduced jitter characteristics

AU - Lee, Myoung Su

AU - Cheung, Tae Sik

AU - Choi, Woo Young

PY - 1999

Y1 - 1999

N2 - A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation.

AB - A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation.

UR - http://www.scopus.com/inward/record.url?scp=85009056063&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85009056063&partnerID=8YFLogxK

U2 - 10.1109/ICVC.1999.821010

DO - 10.1109/ICVC.1999.821010

M3 - Conference contribution

AN - SCOPUS:85009056063

SN - 0780357272

SN - 9780780357273

T3 - ICVC 1999 - 6th International Conference on VLSI and CAD

SP - 596

EP - 598

BT - ICVC 1999 - 6th International Conference on VLSI and CAD

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th International Conference on VLSI and CAD, ICVC 1999

Y2 - 26 October 1999 through 27 October 1999

ER -

A novel charge pump PLL with reduced jitter characteristics

Abstract

Publication series

Other

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this