A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash

Jun Ho An; Hyun Kook Park; Tae Woo Oh; Seong Ook Jung

A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash

Jun Ho An, Hyun Kook Park, Tae Woo Oh, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

High capacity design in NAND Flash has become one of the important issues due to increasing demand for memory capacity expansion. As the number of blocks in NAND Flash increases for high capacity, the driving time of bitline (BL) increases with a large RC, which should be resolved for high capacity NAND Flash. This paper proposes a both-sided BL driving scheme (BSBLDS) for high capacity NAND Flash to achieve a fast driving operation by using an area-optimal NMOS at the far side of the BL. In the conventional one-sided BL driving scheme, the BL driving takes a long time because the current of the BL far node is significantly smaller than that of the BL near node. In the proposed BSBLDS, the both-sided BL overdriving and discharging modes are respectively implemented for fast precharge and discharge operations. The proposed BSBLDS achieves 180% faster precharge speed and 190% faster discharge speed than the conventional driving scheme.

Original language	English
Title of host publication	ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	384-388
Number of pages	5
ISBN (Electronic)	9784885523281
Publication status	Published - 2020 Jul
Event	35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan Duration: 2020 Jul 3 → 2020 Jul 6

Publication series

Name	ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference	35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
Country/Territory	Japan
City	Nagoya
Period	20/7/3 → 20/7/6

Bibliographical note

Publisher Copyright:
© 2020 IEICE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture
Information Systems and Management
Electrical and Electronic Engineering

Cite this

An, J. H., Kook Park, H., Oh, T. W., & Jung, S. O. (2020). A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash. In ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications (pp. 384-388). Article 9183308 (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications). Institute of Electrical and Electronics Engineers Inc..

An, Jun Ho ; Kook Park, Hyun ; Oh, Tae Woo et al. / A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash. ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 384-388 (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications).

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title = "A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash",

abstract = "High capacity design in NAND Flash has become one of the important issues due to increasing demand for memory capacity expansion. As the number of blocks in NAND Flash increases for high capacity, the driving time of bitline (BL) increases with a large RC, which should be resolved for high capacity NAND Flash. This paper proposes a both-sided BL driving scheme (BSBLDS) for high capacity NAND Flash to achieve a fast driving operation by using an area-optimal NMOS at the far side of the BL. In the conventional one-sided BL driving scheme, the BL driving takes a long time because the current of the BL far node is significantly smaller than that of the BL near node. In the proposed BSBLDS, the both-sided BL overdriving and discharging modes are respectively implemented for fast precharge and discharge operations. The proposed BSBLDS achieves 180% faster precharge speed and 190% faster discharge speed than the conventional driving scheme.",

author = "An, {Jun Ho} and {Kook Park}, Hyun and Oh, {Tae Woo} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2020 IEICE.; 35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 ; Conference date: 03-07-2020 Through 06-07-2020",

year = "2020",

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language = "English",

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An, JH, Kook Park, H, Oh, TW & Jung, SO 2020, A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash. in ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications., 9183308, ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications, Institute of Electrical and Electronics Engineers Inc., pp. 384-388, 35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020, Nagoya, Japan, 20/7/3.

A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash. / An, Jun Ho; Kook Park, Hyun; Oh, Tae Woo et al.
ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., 2020. p. 384-388 9183308 (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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An JH, Kook Park H, Oh TW, Jung SO. A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash. In ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc. 2020. p. 384-388. 9183308. (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications).

A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

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