A new static test of a DAC with a built-in structure

Incheol Kim; Jaewon Jang; Hyeonuk Son; Sungho Kang

doi:10.1109/MWSCAS.2011.6026361

A new static test of a DAC with a built-in structure

Incheol Kim, Jaewon Jang, Hyeonuk Son, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new BIST (Built-In Self-Test) scheme to test static parameters of a DAC (Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL (Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.

Original language	English
Title of host publication	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs	https://doi.org/10.1109/MWSCAS.2011.6026361
Publication status	Published - 2011
Event	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of Duration: 2011 Aug 7 → 2011 Aug 10

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Other

Other	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Country/Territory	Korea, Republic of
City	Seoul
Period	11/8/7 → 11/8/10

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2011.6026361

Cite this

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title = "A new static test of a DAC with a built-in structure",

abstract = "A new BIST (Built-In Self-Test) scheme to test static parameters of a DAC (Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL (Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.",

author = "Incheol Kim and Jaewon Jang and Hyeonuk Son and Sungho Kang",

year = "2011",

doi = "10.1109/MWSCAS.2011.6026361",

language = "English",

isbn = "9781612848570",

series = "Midwest Symposium on Circuits and Systems",

booktitle = "54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011",

note = "54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 ; Conference date: 07-08-2011 Through 10-08-2011",

}

Kim, I, Jang, J, Son, H & Kang, S 2011, A new static test of a DAC with a built-in structure. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026361, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 11/8/7. https://doi.org/10.1109/MWSCAS.2011.6026361

TY - GEN

T1 - A new static test of a DAC with a built-in structure

AU - Kim, Incheol

AU - Jang, Jaewon

AU - Son, Hyeonuk

AU - Kang, Sungho

PY - 2011

Y1 - 2011

N2 - A new BIST (Built-In Self-Test) scheme to test static parameters of a DAC (Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL (Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.

AB - A new BIST (Built-In Self-Test) scheme to test static parameters of a DAC (Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL (Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.

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U2 - 10.1109/MWSCAS.2011.6026361

DO - 10.1109/MWSCAS.2011.6026361

M3 - Conference contribution

AN - SCOPUS:80053620976

SN - 9781612848570

T3 - Midwest Symposium on Circuits and Systems

BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011

T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011

Y2 - 7 August 2011 through 10 August 2011

ER -

A new static test of a DAC with a built-in structure

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