A new low power test pattern generator using a transition monitoring window based on BIST architecture

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the proposed BIST TPG schemes can reduce scan transition by about 60% without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.