A new low power test pattern generator for BIST architecture

Kicheol Kim, Dongsub Song, Incheol Kim, Sungho Kang

Research output: Contribution to journalArticlepeer-review


A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.

Original languageEnglish
Pages (from-to)2037-2038
Number of pages2
JournalIEICE Transactions on Electronics
Issue number10
Publication statusPublished - 2005 Oct

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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