A new low power test pattern generator for BIST architecture

Kicheol Kim; Dongsub Song; Incheol Kim; Sungho Kang

doi:10.1093/ietele/e88-c.10.2037

A new low power test pattern generator for BIST architecture

Kicheol Kim, Dongsub Song, Incheol Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.

Original language	English
Pages (from-to)	2037-2038
Number of pages	2
Journal	IEICE Transactions on Electronics
Volume	E88-C
Issue number	10
DOIs	https://doi.org/10.1093/ietele/e88-c.10.2037
Publication status	Published - 2005 Oct

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1093/ietele/e88-c.10.2037

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A new low power test pattern generator for BIST architecture

Abstract

All Science Journal Classification (ASJC) codes

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