A new floating-point normalization scheme by bit parallel operation of leading one position value

Kyung Nam Han; Sang Wook Han; Euisik Yoon

doi:10.1109/APASIC.2002.1031572

A new floating-point normalization scheme by bit parallel operation of leading one position value

Kyung Nam Han, Sang Wook Han, Euisik Yoon

Yonsei Advanced Science Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

In this paper, a new normalization design method for a floating-point unit is presented. Shift amount information for normalization is devised to generate leading one position value (LOPV). LOPV is the number with all zero bits except the leading one position. LOPV can be easily generated by two NOR planes, which implies it can be implemented by bit-parallel operations. Therefore, LOPV can be acquired within about a half delay time of conventional leading zero counters (LZC). An additional NOR plane is required to decode the LOPV to shifter control signals. A total of three NOR planes and an actual shifter operation can implement the floating-point normalization. The chip has been fabricated by using a commercial TSMC 0.18 μm 5-metal CMOS technology with 1.8 V supply voltage. The core area is 550 μm x 200 μm and normalization delay has been measured as 1.4 ns.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	221-224
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031572
Publication status	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China Duration: 2002 Aug 6 → 2002 Aug 8

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan, Province of China
City	Taipei
Period	02/8/6 → 02/8/8

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/APASIC.2002.1031572

Cite this

Han, K. N., Han, S. W., & Yoon, E. (2002). A new floating-point normalization scheme by bit parallel operation of leading one position value. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 221-224). Article 1031572 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031572

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abstract = "In this paper, a new normalization design method for a floating-point unit is presented. Shift amount information for normalization is devised to generate leading one position value (LOPV). LOPV is the number with all zero bits except the leading one position. LOPV can be easily generated by two NOR planes, which implies it can be implemented by bit-parallel operations. Therefore, LOPV can be acquired within about a half delay time of conventional leading zero counters (LZC). An additional NOR plane is required to decode the LOPV to shifter control signals. A total of three NOR planes and an actual shifter operation can implement the floating-point normalization. The chip has been fabricated by using a commercial TSMC 0.18 μm 5-metal CMOS technology with 1.8 V supply voltage. The core area is 550 μm x 200 μm and normalization delay has been measured as 1.4 ns.",

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Han, KN, Han, SW & Yoon, E 2002, A new floating-point normalization scheme by bit parallel operation of leading one position value. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031572, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 221-224, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, Province of China, 02/8/6. https://doi.org/10.1109/APASIC.2002.1031572

A new floating-point normalization scheme by bit parallel operation of leading one position value. / Han, Kyung Nam; Han, Sang Wook; Yoon, Euisik.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 221-224 1031572 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Han KN, Han SW, Yoon E. A new floating-point normalization scheme by bit parallel operation of leading one position value. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 221-224. 1031572. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). doi: 10.1109/APASIC.2002.1031572

A new floating-point normalization scheme by bit parallel operation of leading one position value

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