A new DSP architecture for correcting errors using viterbi algorithm

Sungchul Yoon; Sangwook Kim; Jaeseuk Oh; Sungho Kang

doi:10.1007/3-540-45639-2_10

A new DSP architecture for correcting errors using viterbi algorithm

Sungchul Yoon, Sangwook Kim, Jaeseuk Oh, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Due to the development of wireless internet and an increasing number of internet users, transferring and receiving errorless data in realtime can be the most important method to guarantee the QoS (Quality of Service) of internet. Convolutional encoding and Viterbi decoding are the widely used techniques to enhance the performance of BER (bit error rate) in the application area such as satellite communications systems. As a method to enhance the QoS of internet, a new DSP architecture that can effectively materialize the Viterbi algorithm, one of the algorithms that can correct errors during data transfer, is introduced in this paper. A new architecture and a new instruction set, which can handle the Viterbi algorithm faster, and simplify the Euclidean distance calculation, are defined. The performance assessment result shows that the proposed DSP can execute the Viterbi algorithm faster than other DSPs. Using 0.18 μm CMOS technology, the new DSP operates in 100 MHz, and consumes 218 μA/MHz.

Original language	English
Title of host publication	Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings
Editors	Whie Chang
Publisher	Springer Verlag
Pages	95-102
Number of pages	8
ISBN (Print)	3540439684, 9783540439684
DOIs	https://doi.org/10.1007/3-540-45639-2_10
Publication status	Published - 2002
Event	1st International Workshop on Advanced Internet Services and Applications, AISA 2002 - Seoul, Korea, Republic of Duration: 2002 Aug 1 → 2002 Aug 2

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2402
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	1st International Workshop on Advanced Internet Services and Applications, AISA 2002
Country/Territory	Korea, Republic of
City	Seoul
Period	02/8/1 → 02/8/2

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2002.

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/3-540-45639-2_10

Cite this

Yoon, S., Kim, S., Oh, J., & Kang, S. (2002). A new DSP architecture for correcting errors using viterbi algorithm. In W. Chang (Ed.), Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings (pp. 95-102). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2402). Springer Verlag. https://doi.org/10.1007/3-540-45639-2_10

Yoon, Sungchul ; Kim, Sangwook ; Oh, Jaeseuk et al. / A new DSP architecture for correcting errors using viterbi algorithm. Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings. editor / Whie Chang. Springer Verlag, 2002. pp. 95-102 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Due to the development of wireless internet and an increasing number of internet users, transferring and receiving errorless data in realtime can be the most important method to guarantee the QoS (Quality of Service) of internet. Convolutional encoding and Viterbi decoding are the widely used techniques to enhance the performance of BER (bit error rate) in the application area such as satellite communications systems. As a method to enhance the QoS of internet, a new DSP architecture that can effectively materialize the Viterbi algorithm, one of the algorithms that can correct errors during data transfer, is introduced in this paper. A new architecture and a new instruction set, which can handle the Viterbi algorithm faster, and simplify the Euclidean distance calculation, are defined. The performance assessment result shows that the proposed DSP can execute the Viterbi algorithm faster than other DSPs. Using 0.18 μm CMOS technology, the new DSP operates in 100 MHz, and consumes 218 μA/MHz.",

author = "Sungchul Yoon and Sangwook Kim and Jaeseuk Oh and Sungho Kang",

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Yoon, S, Kim, S, Oh, J & Kang, S 2002, A new DSP architecture for correcting errors using viterbi algorithm. in W Chang (ed.), Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2402, Springer Verlag, pp. 95-102, 1st International Workshop on Advanced Internet Services and Applications, AISA 2002, Seoul, Korea, Republic of, 02/8/1. https://doi.org/10.1007/3-540-45639-2_10

A new DSP architecture for correcting errors using viterbi algorithm. / Yoon, Sungchul; Kim, Sangwook; Oh, Jaeseuk et al.
Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings. ed. / Whie Chang. Springer Verlag, 2002. p. 95-102 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2402).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Yoon S, Kim S, Oh J, Kang S. A new DSP architecture for correcting errors using viterbi algorithm. In Chang W, editor, Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings. Springer Verlag. 2002. p. 95-102. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-45639-2_10

A new DSP architecture for correcting errors using viterbi algorithm

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Bibliographical note

All Science Journal Classification (ASJC) codes

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