Due to the development of wireless internet and an increasing number of internet users, transferring and receiving errorless data in realtime can be the most important method to guarantee the QoS (Quality of Service) of internet. Convolutional encoding and Viterbi decoding are the widely used techniques to enhance the performance of BER (bit error rate) in the application area such as satellite communications systems. As a method to enhance the QoS of internet, a new DSP architecture that can effectively materialize the Viterbi algorithm, one of the algorithms that can correct errors during data transfer, is introduced in this paper. A new architecture and a new instruction set, which can handle the Viterbi algorithm faster, and simplify the Euclidean distance calculation, are defined. The performance assessment result shows that the proposed DSP can execute the Viterbi algorithm faster than other DSPs. Using 0.18 μm CMOS technology, the new DSP operates in 100 MHz, and consumes 218 μA/MHz.
|Title of host publication||Advanced Internet Services and Applications - 1st International Workshop, AISA 2002, Proceedings|
|Number of pages||8|
|ISBN (Print)||3540439684, 9783540439684|
|Publication status||Published - 2002|
|Event||1st International Workshop on Advanced Internet Services and Applications, AISA 2002 - Seoul, Korea, Republic of|
Duration: 2002 Aug 1 → 2002 Aug 2
|Name||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|
|Other||1st International Workshop on Advanced Internet Services and Applications, AISA 2002|
|Country/Territory||Korea, Republic of|
|Period||02/8/1 → 02/8/2|
Bibliographical notePublisher Copyright:
© Springer-Verlag Berlin Heidelberg 2002.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)