A new charge pump PLL with reduced jitter

Yu Gun Kim; Myoung Su Lee; Woo Young Choi

A new charge pump PLL with reduced jitter

Yu Gun Kim, Myoung Su Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 μm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

Original language	English
Pages (from-to)	1680-1682
Number of pages	3
Journal	IEICE Transactions on Communications
Volume	E84-B
Issue number	6
Publication status	Published - 2001 Jun

All Science Journal Classification (ASJC) codes

Software
Computer Networks and Communications
Electrical and Electronic Engineering

Cite this

@article{173c38e4c65f466aab8485d924e6905b,

title = "A new charge pump PLL with reduced jitter",

abstract = "A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 μm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.",

author = "Kim, {Yu Gun} and Lee, {Myoung Su} and Choi, {Woo Young}",

year = "2001",

month = jun,

language = "English",

volume = "E84-B",

pages = "1680--1682",

journal = "IEICE Transactions on Communications",

issn = "0916-8516",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "6",

}

TY - JOUR

T1 - A new charge pump PLL with reduced jitter

AU - Kim, Yu Gun

AU - Lee, Myoung Su

AU - Choi, Woo Young

PY - 2001/6

Y1 - 2001/6

N2 - A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 μm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

AB - A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 μm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

UR - http://www.scopus.com/inward/record.url?scp=0035367593&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035367593&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0035367593

SN - 0916-8516

VL - E84-B

SP - 1680

EP - 1682

JO - IEICE Transactions on Communications

JF - IEICE Transactions on Communications

IS - 6

ER -

A new charge pump PLL with reduced jitter

Abstract

All Science Journal Classification (ASJC) codes

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