A new built-in redundancy analysis algorithm based on multiple memory blocks

Jooyoung Kim; Keewon Cho; Woosung Lee; Sungho Kang

doi:10.1109/ISOCC.2015.7401691

A new built-in redundancy analysis algorithm based on multiple memory blocks

Jooyoung Kim, Keewon Cho, Woosung Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.

Original language	English
Title of host publication	ISOCC 2015 - International SoC Design Conference
Subtitle of host publication	SoC for Internet of Everything (IoE)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	43-44
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2015.7401691
Publication status	Published - 2016 Feb 8
Event	12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2015 Nov 2 → 2015 Nov 5

Publication series

Name	ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Other

Other	12th International SoC Design Conference, ISOCC 2015
Country/Territory	Korea, Republic of
City	Gyeongju
Period	15/11/2 → 15/11/5

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2015.7401691

Cite this

Kim, J., Cho, K., Lee, W., & Kang, S. (2016). A new built-in redundancy analysis algorithm based on multiple memory blocks. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) (pp. 43-44). [7401691] (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2015.7401691

Kim, Jooyoung ; Cho, Keewon ; Lee, Woosung et al. / A new built-in redundancy analysis algorithm based on multiple memory blocks. ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. pp. 43-44 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

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title = "A new built-in redundancy analysis algorithm based on multiple memory blocks",

abstract = "With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.",

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Kim, J, Cho, K, Lee, W & Kang, S 2016, A new built-in redundancy analysis algorithm based on multiple memory blocks. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401691, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), Institute of Electrical and Electronics Engineers Inc., pp. 43-44, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 15/11/2. https://doi.org/10.1109/ISOCC.2015.7401691

A new built-in redundancy analysis algorithm based on multiple memory blocks. / Kim, Jooyoung; Cho, Keewon; Lee, Woosung et al.
ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. p. 43-44 7401691 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Kim J, Cho K, Lee W, Kang S. A new built-in redundancy analysis algorithm based on multiple memory blocks. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc. 2016. p. 43-44. 7401691. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). doi: 10.1109/ISOCC.2015.7401691

A new built-in redundancy analysis algorithm based on multiple memory blocks

Abstract

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