A new built-in redundancy analysis algorithm based on multiple memory blocks

Jooyoung Kim, Keewon Cho, Woosung Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Feb 8
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2015 Nov 22015 Nov 5

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)


Other12th International SoC Design Conference, ISOCC 2015
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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