A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors

Woo Chen Park; Kil Whan Lee; Il San Kim; Tack Don Han; Sung Bong Yang

doi:10.1109/ASAP.2002.1030717

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors

Woo Chen Park, Kil Whan Lee, Il San Kim, Tack Don Han, Sung Bong Yang

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
Editors	Robert Schreiber, Shuvra Bhattacharyya, Neil Burgess, Michael Schulte
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	173-182
Number of pages	10
ISBN (Electronic)	0769517129
DOIs	https://doi.org/10.1109/ASAP.2002.1030717
Publication status	Published - 2002
Event	IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States Duration: 2002 Jul 17 → 2002 Jul 19

Publication series

Name	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume	2002-January
ISSN (Print)	1063-6862

Other

Other	IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
Country/Territory	United States
City	San Jose
Period	02/7/17 → 02/7/19

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Computer Networks and Communications

Access to Document

10.1109/ASAP.2002.1030717

Cite this

Park, W. C., Lee, K. W., Kim, I. S., Han, T. D., & Yang, S. B. (2002). A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. In R. Schreiber, S. Bhattacharyya, N. Burgess, & M. Schulte (Eds.), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 (pp. 173-182). [1030717] (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2002.1030717

Park, Woo Chen ; Lee, Kil Whan ; Kim, Il San et al. / A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. editor / Robert Schreiber ; Shuvra Bhattacharyya ; Neil Burgess ; Michael Schulte. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 173-182 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).

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abstract = "As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.",

author = "Park, {Woo Chen} and Lee, {Kil Whan} and Kim, {Il San} and Han, {Tack Don} and Yang, {Sung Bong}",

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Park, WC, Lee, KW, Kim, IS, Han, TD & Yang, SB 2002, A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. in R Schreiber, S Bhattacharyya, N Burgess & M Schulte (eds), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002., 1030717, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 173-182, IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002, San Jose, United States, 02/7/17. https://doi.org/10.1109/ASAP.2002.1030717

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. / Park, Woo Chen; Lee, Kil Whan; Kim, Il San et al.
Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. ed. / Robert Schreiber; Shuvra Bhattacharyya; Neil Burgess; Michael Schulte. Institute of Electrical and Electronics Engineers Inc., 2002. p. 173-182 1030717 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.

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Park WC, Lee KW, Kim IS, Han TD , Yang SB. A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. In Schreiber R, Bhattacharyya S, Burgess N, Schulte M, editors, Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 173-182. 1030717. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). doi: 10.1109/ASAP.2002.1030717

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors

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