As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.
|Title of host publication||Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002|
|Editors||Robert Schreiber, Shuvra Bhattacharyya, Neil Burgess, Michael Schulte|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||10|
|Publication status||Published - 2002|
|Event||IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States|
Duration: 2002 Jul 17 → 2002 Jul 19
|Name||Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors|
|Other||IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002|
|Period||02/7/17 → 02/7/19|
Bibliographical notePublisher Copyright:
© 2002 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications