A Memory Based Concurrence Detector for SPAD ToF Image Sensors

Jongha Park; Seong Ook Jung

doi:10.1109/ITC-CSCC58803.2023.10212957

A Memory Based Concurrence Detector for SPAD ToF Image Sensors

Jongha Park
, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work presents an area efficient memory based concurrence detector (MCD) for Time-of-flight (ToF) image sensors. The proposed MCD consists of four 10-bit registers, register selector and a coarse bit comparator. 4 × 4 pixel array of MCD based single-photon avalanche diode (SPAD) histogramming circuit is implemented in 0.18 μm CMOS process with an area of 970μm X 124 μm, 59% less area compared to the conventional 4-pixel concurrence detector(CD) based SPAD histogramming circuit. Peak to background ratio and peak count rate are improved by X 0.13 and X 2.4 respectively, compared to the conventional 4-pixel CD based SPAD histogramming circuit.

Original language	English
Title of host publication	2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350326413
DOIs	https://doi.org/10.1109/ITC-CSCC58803.2023.10212957
Publication status	Published - 2023
Event	2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023 - Jeju, Korea, Republic of Duration: 2023 Jun 25 → 2023 Jun 28

Publication series

Name	2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023

Conference

Conference	2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	23/6/25 → 23/6/28

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Computer Graphics and Computer-Aided Design
Computer Networks and Communications
Computer Science Applications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ITC-CSCC58803.2023.10212957

Cite this

Park, J., & Jung, S. O. (2023). A Memory Based Concurrence Detector for SPAD ToF Image Sensors. In 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023 (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC58803.2023.10212957

Park, Jongha ; Jung, Seong Ook. / A Memory Based Concurrence Detector for SPAD ToF Image Sensors. 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023).

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title = "A Memory Based Concurrence Detector for SPAD ToF Image Sensors",

abstract = "This work presents an area efficient memory based concurrence detector (MCD) for Time-of-flight (ToF) image sensors. The proposed MCD consists of four 10-bit registers, register selector and a coarse bit comparator. 4 × 4 pixel array of MCD based single-photon avalanche diode (SPAD) histogramming circuit is implemented in 0.18 μm CMOS process with an area of 970μm X 124 μm, 59\% less area compared to the conventional 4-pixel concurrence detector(CD) based SPAD histogramming circuit. Peak to background ratio and peak count rate are improved by X 0.13 and X 2.4 respectively, compared to the conventional 4-pixel CD based SPAD histogramming circuit.",

author = "Jongha Park and Jung, \{Seong Ook\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023 ; Conference date: 25-06-2023 Through 28-06-2023",

year = "2023",

doi = "10.1109/ITC-CSCC58803.2023.10212957",

language = "English",

series = "2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023",

address = "United States",

}

Park, J & Jung, SO 2023, A Memory Based Concurrence Detector for SPAD ToF Image Sensors. in 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023, Institute of Electrical and Electronics Engineers Inc., 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023, Jeju, Korea, Republic of, 23/6/25. https://doi.org/10.1109/ITC-CSCC58803.2023.10212957

A Memory Based Concurrence Detector for SPAD ToF Image Sensors. / Park, Jongha; Jung, Seong Ook.
2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Park, Jongha

AU - Jung, Seong Ook

PY - 2023

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N2 - This work presents an area efficient memory based concurrence detector (MCD) for Time-of-flight (ToF) image sensors. The proposed MCD consists of four 10-bit registers, register selector and a coarse bit comparator. 4 × 4 pixel array of MCD based single-photon avalanche diode (SPAD) histogramming circuit is implemented in 0.18 μm CMOS process with an area of 970μm X 124 μm, 59% less area compared to the conventional 4-pixel concurrence detector(CD) based SPAD histogramming circuit. Peak to background ratio and peak count rate are improved by X 0.13 and X 2.4 respectively, compared to the conventional 4-pixel CD based SPAD histogramming circuit.

AB - This work presents an area efficient memory based concurrence detector (MCD) for Time-of-flight (ToF) image sensors. The proposed MCD consists of four 10-bit registers, register selector and a coarse bit comparator. 4 × 4 pixel array of MCD based single-photon avalanche diode (SPAD) histogramming circuit is implemented in 0.18 μm CMOS process with an area of 970μm X 124 μm, 59% less area compared to the conventional 4-pixel concurrence detector(CD) based SPAD histogramming circuit. Peak to background ratio and peak count rate are improved by X 0.13 and X 2.4 respectively, compared to the conventional 4-pixel CD based SPAD histogramming circuit.

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M3 - Conference contribution

AN - SCOPUS:85169833010

T3 - 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023

BT - 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023

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Park J, Jung SO. A Memory Based Concurrence Detector for SPAD ToF Image Sensors. In 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023). doi: 10.1109/ITC-CSCC58803.2023.10212957

A Memory Based Concurrence Detector for SPAD ToF Image Sensors

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