Abstract
A low-voltage phase-locked loop (PLL) circuit having a charge pump (CP) with a novel negative feedback replica bias scheme for current mismatch compensation is demonstrated. A prototype 400-MHz PLL circuit operating at 0.65-V is fabricated with 180-nm standard CMOS process. Measurement results show that current mismatch compensation is successfully achieved. Our PLL consumes only 140-μW.
Original language | English |
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Title of host publication | ISOCC 2015 - International SoC Design Conference |
Subtitle of host publication | SoC for Internet of Everything (IoE) |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 15-16 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
Publication status | Published - 2016 Feb 8 |
Event | 12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2015 Nov 2 → 2015 Nov 5 |
Publication series
Name | ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) |
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Other
Other | 12th International SoC Design Conference, ISOCC 2015 |
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Country/Territory | Korea, Republic of |
City | Gyeongju |
Period | 15/11/2 → 15/11/5 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials