A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

Taeryeong Kim; Ji Young Kim; Jeonghyeok You; Hohyun Chae; Byoung Mo Moon; Kyomin Sohn; Seong Ook Jung

doi:10.23919/VLSITechnologyandCir57934.2023.10185328

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

Taeryeong Kim
, Ji Young Kim
, Jeonghyeok You
, Hohyun Chae
, Byoung Mo Moon
, Kyomin Sohn
, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER < 10-12 at 15Gb/s with PRBS-31.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185328
Publication status	Published - 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 2023 Jun 11 → 2023 Jun 16

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	23/6/11 → 23/6/16

Bibliographical note

Publisher Copyright:
© 2023 JSAP.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185328

Cite this

Kim, T., Kim, J. Y., You, J., Chae, H., Moon, B. M., Sohn, K., & Jung, S. O. (2023). A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185328

Kim, Taeryeong ; Kim, Ji Young ; You, Jeonghyeok et al. / A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC",

abstract = "This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30\% timing margin with BER < 10-12 at 15Gb/s with PRBS-31.",

author = "Taeryeong Kim and Kim, \{Ji Young\} and Jeonghyeok You and Hohyun Chae and Moon, \{Byoung Mo\} and Kyomin Sohn and Jung, \{Seong Ook\}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185328",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023",

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Kim, T, Kim, JY, You, J, Chae, H, Moon, BM, Sohn, K & Jung, SO 2023, A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 23/6/11. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185328

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. / Kim, Taeryeong; Kim, Ji Young; You, Jeonghyeok et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Taeryeong

AU - Kim, Ji Young

AU - You, Jeonghyeok

AU - Chae, Hohyun

AU - Moon, Byoung Mo

AU - Sohn, Kyomin

AU - Jung, Seong Ook

PY - 2023

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N2 - This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER < 10-12 at 15Gb/s with PRBS-31.

AB - This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER < 10-12 at 15Gb/s with PRBS-31.

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M3 - Conference contribution

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BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

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Kim T, Kim JY, You J, Chae H, Moon BM, Sohn K et al. A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185328

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

All Science Journal Classification (ASJC) codes

Access to Document

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