A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

Ji Young Kim; Taeryeong Kim; Jeonghyeok You; Kiryong Kim; Byoung Mo Moon; Kyomin Sohn; Seong Ook Jung

doi:10.1109/VLSITechnologyandCir46769.2022.9830160

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

Ji Young Kim, Taeryeong Kim, Jeonghyeok You, Kiryong Kim, Byoung Mo Moon, Kyomin Sohn, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A low power through-silicon via (TSV) I/O for the high-bandwidth memory is proposed with a 65nm CMOS process. The proposed TSV I/O, which employs a low-supply voltage for low-power operation, consists of a 4-to-1 multiplexer (MUX) with replica MUX, pre-driver that realizes pre-emphasis without static power consumption, and digitally calibrated 1-to-4 de-MUX comparator. The measured energy efficiency is 0.179-0.185pJ/b/pF with a PRBS-31 at 5-10Gb/s.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	152-153
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830160
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 2022 Jun 12 → 2022 Jun 17

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	22/6/12 → 22/6/17

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSITechnologyandCir46769.2022.9830160

Cite this

Kim, J. Y., Kim, T., You, J., Kim, K., Moon, B. M., Sohn, K., & Jung, S. O. (2022). A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 152-153). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830160

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title = "A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM",

abstract = "A low power through-silicon via (TSV) I/O for the high-bandwidth memory is proposed with a 65nm CMOS process. The proposed TSV I/O, which employs a low-supply voltage for low-power operation, consists of a 4-to-1 multiplexer (MUX) with replica MUX, pre-driver that realizes pre-emphasis without static power consumption, and digitally calibrated 1-to-4 de-MUX comparator. The measured energy efficiency is 0.179-0.185pJ/b/pF with a PRBS-31 at 5-10Gb/s.",

author = "Kim, {Ji Young} and Taeryeong Kim and Jeonghyeok You and Kiryong Kim and Moon, {Byoung Mo} and Kyomin Sohn and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830160",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

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Kim, JY, Kim, T, You, J, Kim, K, Moon, BM, Sohn, K & Jung, SO 2022, A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 152-153, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 22/6/12. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830160

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. / Kim, Ji Young; Kim, Taeryeong; You, Jeonghyeok et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 152-153 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kim, Ji Young

AU - Kim, Taeryeong

AU - You, Jeonghyeok

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AB - A low power through-silicon via (TSV) I/O for the high-bandwidth memory is proposed with a 65nm CMOS process. The proposed TSV I/O, which employs a low-supply voltage for low-power operation, consists of a 4-to-1 multiplexer (MUX) with replica MUX, pre-driver that realizes pre-emphasis without static power consumption, and digitally calibrated 1-to-4 de-MUX comparator. The measured energy efficiency is 0.179-0.185pJ/b/pF with a PRBS-31 at 5-10Gb/s.

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Kim JY, Kim T, You J, Kim K, Moon BM, Sohn K et al. A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 152-153. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830160

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

Access to Document

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