A low-power packet memory architecture with a latency-aware packet mapping method

Hyuk Jun Lee, Seung Chul Kim, Eui Young Chung

Research output: Contribution to journalArticlepeer-review


A packet memory stores packets in internet routers and it requires typically RTT ×C for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to RTT×C/√N, where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.

Original languageEnglish
Pages (from-to)963-966
Number of pages4
JournalIEICE Transactions on Information and Systems
Issue number4
Publication statusPublished - 2013 Apr

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


Dive into the research topics of 'A low-power packet memory architecture with a latency-aware packet mapping method'. Together they form a unique fingerprint.

Cite this