A low-power cache system for embedded processors

Gi Ho Park, Kil Whan Lee, Jang Soo Lee, Tack Don Han, Shin Dug Kim, Yong Chun Kim, Seh Woong Jeong, Kwang Yup Lee

Research output: Contribution to journalArticlepeer-review


A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

Original languageEnglish
Pages (from-to)316-319
Number of pages4
JournalMidwest Symposium on Circuits and Systems
Publication statusPublished - 2000

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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