A low-power cache system for embedded processors

Gi Ho Park; Kil Whan Lee; Jang Soo Lee; Tack Don Han; Shin Dug Kim; Yong Chun Kim; Seh Woong Jeong; Kwang Yup Lee

doi:10.1109/MWSCAS.2000.951650

A low-power cache system for embedded processors

Gi Ho Park, Kil Whan Lee, Jang Soo Lee, Tack Don Han, Shin Dug Kim, Yong Chun Kim, Seh Woong Jeong, Kwang Yup Lee

College of Computing

Research output: Contribution to journal › Article › peer-review

Abstract

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

Original language	English
Pages (from-to)	316-319
Number of pages	4
Journal	Midwest Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/MWSCAS.2000.951650
Publication status	Published - 2000

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/MWSCAS.2000.951650

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abstract = "A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.",

author = "Park, {Gi Ho} and Lee, {Kil Whan} and Lee, {Jang Soo} and Han, {Tack Don} and Kim, {Shin Dug} and Kim, {Yong Chun} and Jeong, {Seh Woong} and Lee, {Kwang Yup}",

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language = "English",

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AU - Park, Gi Ho

AU - Lee, Kil Whan

AU - Lee, Jang Soo

AU - Han, Tack Don

AU - Kim, Shin Dug

AU - Kim, Yong Chun

AU - Jeong, Seh Woong

AU - Lee, Kwang Yup

PY - 2000

Y1 - 2000

N2 - A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

AB - A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

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SP - 316

EP - 319

JO - Midwest Symposium on Circuits and Systems

JF - Midwest Symposium on Circuits and Systems

ER -

A low-power cache system for embedded processors

Abstract

All Science Journal Classification (ASJC) codes

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