TY - GEN
T1 - A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems
AU - Chang, Sun Il
AU - Yoon, Euisik
PY - 2009
Y1 - 2009
N2 - We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm2. We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 ± 0.47 dB, 57.90 ± 2.82dB, -53.58 ± 2.15 dB, and 6.65 ± 0.07 bits, respectively.
AB - We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm2. We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 ± 0.47 dB, 57.90 ± 2.82dB, -53.58 ± 2.15 dB, and 6.65 ± 0.07 bits, respectively.
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U2 - 10.1109/IEMBS.2009.5333068
DO - 10.1109/IEMBS.2009.5333068
M3 - Conference contribution
C2 - 19963759
AN - SCOPUS:77950979683
SN - 9781424432967
T3 - Proceedings of the 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society: Engineering the Future of Biomedicine, EMBC 2009
SP - 1647
EP - 1650
BT - Proceedings of the 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society
PB - IEEE Computer Society
T2 - 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society: Engineering the Future of Biomedicine, EMBC 2009
Y2 - 2 September 2009 through 6 September 2009
ER -