A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

Dong Hoon Jung; Kyungho Ryu; Jung Hyun Park; Seong Ook Jung

doi:10.1109/ESSCIRC.2012.6341288

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

Dong Hoon Jung, Kyungho Ryu, Jung Hyun Park, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm². The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.

Original language	English
Title of host publication	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages	181-184
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341288
Publication status	Published - 2012
Event	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France Duration: 2012 Sept 17 → 2012 Sept 21

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	38th European Solid State Circuits Conference, ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	12/9/17 → 12/9/21

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2012.6341288

Cite this

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title = "A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction",

abstract = "In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.",

author = "Jung, {Dong Hoon} and Kyungho Ryu and Park, {Jung Hyun} and Jung, {Seong Ook}",

year = "2012",

doi = "10.1109/ESSCIRC.2012.6341288",

language = "English",

isbn = "9781467322126",

series = "European Solid-State Circuits Conference",

pages = "181--184",

booktitle = "2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012",

note = "38th European Solid State Circuits Conference, ESSCIRC 2012 ; Conference date: 17-09-2012 Through 21-09-2012",

}

Jung, DH, Ryu, K, Park, JH & Jung, SO 2012, A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341288, European Solid-State Circuits Conference, pp. 181-184, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 12/9/17. https://doi.org/10.1109/ESSCIRC.2012.6341288

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. / Jung, Dong Hoon; Ryu, Kyungho; Park, Jung Hyun et al.
2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 181-184 6341288 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.

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A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

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