A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

Ge Yang; Seong Ook Jung; Soo Hwan Kim; Sung Mo Kang

A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

Ge Yang, Seong Ook Jung, Soo Hwan Kim, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1 GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.

Original language	English
Pages	II298-II301
Publication status	Published - 2002
Event	2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States Duration: 2002 Aug 4 → 2002 Aug 7

Other

Other	2002 45th Midwest Symposium on Circuits and Systems
Country/Territory	United States
City	Tulsa, OK
Period	02/8/4 → 02/8/7

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic",

abstract = "A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1 GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.",

author = "Ge Yang and Jung, {Seong Ook} and Kim, {Soo Hwan} and Kang, {Sung Mo}",

year = "2002",

language = "English",

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note = "2002 45th Midwest Symposium on Circuits and Systems ; Conference date: 04-08-2002 Through 07-08-2002",

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T1 - A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

AU - Yang, Ge

AU - Jung, Seong Ook

AU - Kim, Soo Hwan

AU - Kang, Sung Mo

PY - 2002

Y1 - 2002

N2 - A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1 GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.

AB - A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1 GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.

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M3 - Paper

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T2 - 2002 45th Midwest Symposium on Circuits and Systems

Y2 - 4 August 2002 through 7 August 2002

ER -

A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

Abstract

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All Science Journal Classification (ASJC) codes

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